1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. In particular, the present invention relates to a charge-trapping type nonvolatile semiconductor memory and a data programming/erasing method for the charge-trapping type nonvolatile semiconductor memory.
2. Description of Related Art
A flash memory and a charge trapping memory are known as an electrically erasable and programmable nonvolatile semiconductor memory. The charge trapping memory among them stores data by using an element that can trap charges. For example, the element for trapping charges is a MONOS (Metal Oxide Nitride Oxide Silicon) transistor. The MONOS transistor is a kind of a MIS (Metal Insulator Silicon) transistor, and its gate insulating film is an ONO (Oxide Nitride Oxide) film formed by stacking a silicon oxide film, a silicon nitride film and a silicon oxide film in this order.
The silicon nitride film in the ONO film has a property of trapping charges. For example, it is possible to inject electrons into the silicon nitride film by applying appropriate voltages respectively to a gate electrode, source/drain and a substrate. In a case where electrons are trapped in the silicon nitride film, a threshold voltage of the MONOS transistor increases as compared with a case where electrons are not trapped. Conversely, the threshold voltage decreases when trapped electrons are ejected from the silicon nitride film. By utilizing such change in the threshold voltage, the MONOS transistor can nonvolatilely store data “1” and “0”. That is to say, the charge trapping memory stores data by using the MONOS transistor as a memory cell.
The followings are known as techniques related to the charge trapping memory.
According to a charge trapping memory described in Japanese Laid Open Patent Application JP-H-05-13776 (Patent Document 1), a surface of a channel region of a MNOS transistor is formed to be convex. When a voltage is applied between a gate electrode and the channel region, an electric field is intensified at the convex section. As a result, a voltage at the time of programming/erasing can be reduced.
Japanese Laid Open Patent Applications JP-2002-289711 (Patent Document 2), JP-2003-163292 (Patent Document 3) and JP-2001-102466 (Patent Document 4) each disclose a charge trapping memory that uses a memory cell transistor having a plurality of gate electrodes. Typically, the memory cell transistor has one word gate and two control gates provided on both sides of the word gate. An ONO film is formed between each control gate and a semiconductor substrate. In this case, one memory cell is capable of storing 2-bit data. The charge trapping memory having such a structure is also referred to as a “twin-MONOS-type memory”.
According to the above-mentioned Patent Document 4 (JP-2001-102466), the electron injection into the silicon nitride film is performed by “CHE (Channel Hot Electron) method”. That is, channel hot electrons generated in the vicinity of a drain in the semiconductor substrate are injected into the silicon nitride film from the semiconductor substrate side. On the other hand, the electron ejection from the silicon nitride film is performed by “FN (Fowler-Nordheim) tunneling method”. Here, electrons are ejected from the silicon nitride film to the control gate side by the FN tunneling.
In either case of the CHE method and the FN tunneling method, a predetermined voltage needs to be applied to the control gate. In general, an absolute value of the applied voltage is larger in the case of the FN tunneling method than in the case of the CHE method. In the case of the FN tunneling method, the applied voltage is comparatively high and thus a breakdown voltage required for the memory cell transistor is also comparatively high. This causes increase in the element size.
The inventor of the present application has recognized the following points. That is a fact that a greater amount of current is required in the CHE method than in the FN tunneling method. More specifically, the amount of current is several tens pA (picoampere) in the case of the FN tunneling method, while it is several hundreds μA (microampere) in the case of the CHE method.
In the case of the CHE method, the channel is conducting and the current flows between the drain and the source. Then, only a part of electrons of the current is stochastically injected into the silicon nitride film, and the remaining electrons are drawn into the drain. In the case of the FN tunneling method, on the other hand, the channel is not conducting and a current does not flow between the drain and the source. Electrons are transferred to or from the silicon nitride film through a tunnel insulating film, and only an FN tunnel current associated with the electron transfer flows. As an example, let us consider injection of the same amount of electrons into the silicon nitride film. In this case, an extra current that does not contribute to the electron injection is necessary according to the CHE method, as compared with the FN tunneling method. It can be said that an efficiency of the electron injection with respect to the necessary current is worse in the CHE method than in the FN tunneling method.
As described above, the CHE method requires a large amount of current, which leads to increase in current consumption. Accordingly, a technique is desired which can reduce the current consumption with suppressing the increase in the element size.